Ultra thin silicon on insulator

ABSTRACT

In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of co-pending U.S. patent application Ser. No. 12/042,936, filed Mar. 5, 2008, which is herein incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates generally to high-performance transistors, and relates more particularly to the fabrication of ultra thin silicon on insulators.

Ultra thin silicon on insulator (UTSOI) refers to SOIs having an extremely thin layer of silicon (e.g., forty to eighty Angstroms) deposited on a silicon dioxide (SiO₂) buried oxide (BOX) layer. UTSOI is often used in the fabrication of high-performance transistors.

Due to the extreme thinness of the silicon layer, contact resistance becomes a critical issue. Attempts to reduce contact resistance have included raising the source and drain of the UTSOI, for instance using selective epitaxial silicon or silicon germanide (SiGe) growth. The temperature of the epitaxial growth in such processes is a critical parameter for proper employment of the raised source and drain technique. For instance, if the temperature is too high (e.g. approximately 800 degrees Celsius or above) the thin silicon layer becomes agglomerated and uneven, resulting in greatly increased contact resistance. However, if the temperature is too low (e.g., less than approximately 750 degrees Celsius), selectivity and growth rate prevent good formation of the raised source and drain.

Thus, there is a need in the art for a method and apparatus for fabricating an ultra thin silicon on insulator to reduce contact resistance.

SUMMARY OF THE INVENTION

In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

FIG. 1 is a schematic diagram illustrating an exemplary field effect transistor component of a complementary metal-oxide-semiconductor device, fabricated in accordance with the present invention; and

FIG. 2 is a flow diagram illustrating one embodiment of a method for fabricating an ultra thin silicon on insulator, according to the present invention.

DETAILED DESCRIPTION

In one embodiment, the present invention is a method and apparatus for fabricating an ultra thin silicon on insulator. Embodiments of the invention grow a selective epitaxial silicon (Si) or silicon germanide (SiGe) alloy at a moderate high temperature, resulting in a raised source and drain region with selectivity, high growth rate, and excellent silicon quality. More importantly, the occurrence of silicon agglomeration is greatly reduced.

FIG. 1 is a schematic diagram illustrating an exemplary field effect transistor (FET) component 100 of a complementary metal-oxide-semiconductor (CMOS) device, fabricated in accordance with the present invention. The FET 100 may be an n-type FET (nFET) or a p-type FET (pFET).

The FET 100 comprises a buried oxide (BOX) layer 102 upon which a thin silicon layer 104 and a shallow trench isolation (STI) region 106 are formed. A gate dielectric 108 is formed over at least a portion of the silicon layer 104, and a gate area 110 is formed over the gate dielectric 108. The gate dielectric 108 provides a conductive barrier between the gate area 110 and a raised source/drain region 112 (where the source/drain region 112 is raised with respect to the silicon layer 104).

FIG. 2 is a flow diagram illustrating one embodiment of a method 200 for fabricating an ultra thin silicon on insulator, according to the present invention. The method 200 may be implemented, for example, to fabricate the FET illustrated in FIG. 1.

The method 200 is initialized at step 202 and proceeds to step 204, where the method 200 deposits a thin layer of silicon on a buried oxide layer. In one embodiment, the buried oxide layer comprises silicon dioxide (SiO₂). In one embodiment, the layer of silicon has an initial thickness in the range of approximately forty to approximately eighty Angstroms.

In step 206, the method 200 saturates the silicon layer with reactant gases at a low temperature. In one embodiment, the reactant gases comprise at least one of: dichlorosilane (SiH₂Cl₂), hydrochloric acid (HCl), silane, and a silane compound. In one embodiment, a “low” temperature for the purposes of step 206 is a temperature that is low enough to substantially prevent the occurrence of any reactions involving the reactant gases (e.g., approximately 400 degrees Celsius).

In step 208, the method 200 gradually raises the temperature. As the reactant gases reach their dissociation temperatures (e.g., approximately 650 degrees Celsius), the reactant gases will react and form selective epitaxial silicon on the silicon layer. This selective epitaxial layer forms a raised source and drain region on the silicon layer. For example, the dissociation bonding energy of dichlorosilane is approximately 105 Kcal/mole and the dissociation bonding energy of hydrochloric acid is approximately 103 Kcal/mole. Thus, in the case where both dichlorosilane and hydrochloric acid are used as reactant gases, the reactant gases will dissociate substantially simultaneously to form radicals and to react to the surface of the silicon layer. The method 200 then terminates in step 210.

Because the thin epitaxial silicon forms on the silicon layer (which is no longer as thin as when the method 200 started), silicon agglomeration is substantially prevented. In one embodiment, the combined thickness of the silicon layer and the epitaxial silicon is approximately five to approximately thirty nanometers.

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. Various embodiments presented herein, or portions thereof, may be combined to create further embodiments. Furthermore, terms such as top, side, bottom, front, back, and the like are relative or positional terms and are used with respect to the exemplary embodiments illustrated in the figures, and as such these terms may be interchangeable. 

1. An ultra thin silicon on insulator, comprising: a silicon layer; and a raised source and drain region grown on the silicon layer, the raised source and drain region being grown by: saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the at least one reactant gas; and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the at least one reactant gas.
 2. The ultra thin silicon on insulator of claim 1, wherein the raised source and drain region is formed of silicon or silicon germanide.
 3. The ultra thin silicon on insulator of claim 1, wherein the at least one reactant gas comprises a plurality of reactant gases, the plurality of reactant gases having substantially similar dissociation temperatures.
 4. The ultra thin silicon on insulator of claim 1, wherein the at least one reactant gas comprises at least one of: dichlorosilane, hydrochloric acid, silane, and a silane compound.
 5. The ultra thin silicon on insulator of claim 1, wherein the first temperature is approximately 400 degrees Celsius.
 6. The ultra thin silicon on insulator of claim 1, wherein the second temperature is approximately 650 degrees Celsius.
 7. The ultra thin silicon on insulator of claim 1, wherein the silicon layer has an initial thickness prior to the saturating in the range of approximately forty to approximately eighty Angstroms.
 8. The ultra thin silicon on insulator of claim 1, wherein a combined thickness of the silicon layer and the raised source and drain region is in the range of approximately five to approximately thirty nanometers.
 9. A field effect transistor, comprising: a buried oxide layer; a silicon layer formed over the buried oxide layer; and a raised source and drain region formed on the silicon layer; the raised source and drain region being formed by: saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the at least one reactant gas; and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the at least one reactant gas.
 10. The field effect transistor of claim 9, further comprising: a gate dielectric formed on at least a portion of the silicon layer; and a gate area formed over the gate dielectric, where the gate dielectric provides a conductive barrier between the gate area and the raised source and drain region. 